// generated by newgenasym  Sat Dec 04 12:40:26 2010


module adclk925 (d, d_n, pad, q1, q1_n, q2, q2_n, vcc, vcc1, vee, vee1, vref, vt);
    input d;
    input d_n;
    inout pad;
    output q1;
    output q1_n;
    output q2;
    output q2_n;
    input vcc;
    input vcc1;
    input vee;
    input vee1;
    input vref;
    inout vt;


    initial
        begin
        end

endmodule
