// generated by newgenasym  Mon Jul 12 16:55:16 2010


module ad9517 (bypass, clk, clk_n, cp, cprset, cs_n, ld, lf, out0, out0_n,
        out1, out1_n, out2, out2_n, out3, out3_n, out4_n_out4b,
        out4_out4a, out5_n_out5b, out5_out5a, out6_n_out6b,
        out6_out6a, out7_n_out7b, out7_out7a, pad, pd_n, ref_sel,
        refin_n_ref2, refin_ref1, refmon, reset_n, rset, sclk, sdio,
        sdo, status, sync_n, vcp, vs_1, vs_2, vs_3, vs_4, vs_5, vs_6,
        vs_7, vs_8, vs_9, vs_lvpecl_1, vs_lvpecl_2);
    inout bypass;
    input clk;
    input clk_n;
    output cp;
    inout cprset;
    input cs_n;
    output ld;
    input lf;
    output out0;
    output out0_n;
    output out1;
    output out1_n;
    output out2;
    output out2_n;
    output out3;
    output out3_n;
    output out4_n_out4b;
    output out4_out4a;
    output out5_n_out5b;
    output out5_out5a;
    output out6_n_out6b;
    output out6_out6a;
    output out7_n_out7b;
    output out7_out7a;
    input pad;
    input pd_n;
    input ref_sel;
    input refin_n_ref2;
    input refin_ref1;
    output refmon;
    input reset_n;
    inout rset;
    input sclk;
    inout sdio;
    output sdo;
    output status;
    input sync_n;
    input vcp;
    input vs_1;
    input vs_2;
    input vs_3;
    input vs_4;
    input vs_5;
    input vs_6;
    input vs_7;
    input vs_8;
    input vs_9;
    input vs_lvpecl_1;
    input vs_lvpecl_2;


    initial
        begin
        end

endmodule
