-- generated by newgenasym Mon Nov 05 17:56:09 2012

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity fxla104 is
    port (    
	A0:        INOUT  STD_LOGIC;    
	A1:        INOUT  STD_LOGIC;    
	A2:        INOUT  STD_LOGIC;    
	A3:        INOUT  STD_LOGIC;    
	B0:        INOUT  STD_LOGIC;    
	B1:        INOUT  STD_LOGIC;    
	B2:        INOUT  STD_LOGIC;    
	B3:        INOUT  STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	OE_N:      IN     STD_LOGIC;    
	VCCA:      IN     STD_LOGIC;    
	VCCB:      IN     STD_LOGIC);
end fxla104;
