-- generated by newgenasym Wed Jul 02 16:41:46 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity xfmradt1_1wt_a is
    port (    
	NC5:       INOUT  STD_LOGIC;    
	PRIN:      INOUT  STD_LOGIC;    
	PRIP:      INOUT  STD_LOGIC;    
	SECCT:     INOUT  STD_LOGIC;    
	SECN:      INOUT  STD_LOGIC;    
	SECP:      INOUT  STD_LOGIC);
end xfmradt1_1wt_a;
