-- generated by newgenasym Mon Jun 07 13:33:43 2010

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity adl5380 is
    port (    
	ADJ:       INOUT  STD_LOGIC;    
	ENBL:      IN     STD_LOGIC;    
	GND0:      IN     STD_LOGIC;    
	GND1:      IN     STD_LOGIC;    
	GND2:      IN     STD_LOGIC;    
	GND3:      IN     STD_LOGIC;    
	GND4:      IN     STD_LOGIC;    
	GND5:      IN     STD_LOGIC;    
	GND6:      IN     STD_LOGIC;    
	GND7:      IN     STD_LOGIC;    
	GND8:      IN     STD_LOGIC;    
	GND9:      IN     STD_LOGIC;    
	IHI:       OUT    STD_LOGIC;    
	ILO:       OUT    STD_LOGIC;    
	LOIN:      IN     STD_LOGIC;    
	LOIP:      IN     STD_LOGIC;    
	NC12:      INOUT  STD_LOGIC;    
	PAD:       IN     STD_LOGIC;    
	QHI:       OUT    STD_LOGIC;    
	QLO:       OUT    STD_LOGIC;    
	RFIN:      IN     STD_LOGIC;    
	RFIP:      IN     STD_LOGIC;    
	VCC0:      IN     STD_LOGIC;    
	VCC1:      IN     STD_LOGIC;    
	VCC2:      IN     STD_LOGIC);
end adl5380;
