-- generated by newgenasym Fri Jul 06 13:29:22 2012

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity adm7150 is
    port (    
	BYP:       INOUT  STD_LOGIC;    
	EN:        IN     STD_LOGIC;    
	EP:        IN     STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	REF:       OUT    STD_LOGIC;    
	REF_SENSE: OUT    STD_LOGIC;    
	VIN:       IN     STD_LOGIC;    
	VOUT:      OUT    STD_LOGIC;    
	VREG:      IN     STD_LOGIC);
end adm7150;
