-- generated by newgenasym Sat Dec 04 12:40:26 2010

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity adclk925 is
    port (    
	D:         IN     STD_LOGIC;    
	D_N:       IN     STD_LOGIC;    
	PAD:       INOUT  STD_LOGIC;    
	Q1:        OUT    STD_LOGIC;    
	Q1_N:      OUT    STD_LOGIC;    
	Q2:        OUT    STD_LOGIC;    
	Q2_N:      OUT    STD_LOGIC;    
	VCC:       IN     STD_LOGIC;    
	VCC1:      IN     STD_LOGIC;    
	VEE:       IN     STD_LOGIC;    
	VEE1:      IN     STD_LOGIC;    
	VREF:      IN     STD_LOGIC;    
	VT:        INOUT  STD_LOGIC);
end adclk925;
