-- generated by newgenasym Mon Jul 12 16:55:16 2010

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity ad9517 is
    port (    
	BYPASS:    INOUT  STD_LOGIC;    
	CLK:       IN     STD_LOGIC;    
	CLK_N:     IN     STD_LOGIC;    
	CP:        OUT    STD_LOGIC;    
	CPRSET:    INOUT  STD_LOGIC;    
	CS_N:      IN     STD_LOGIC;    
	LD:        OUT    STD_LOGIC;    
	LF:        IN     STD_LOGIC;    
	OUT0:      OUT    STD_LOGIC;    
	OUT0_N:    OUT    STD_LOGIC;    
	OUT1:      OUT    STD_LOGIC;    
	OUT1_N:    OUT    STD_LOGIC;    
	OUT2:      OUT    STD_LOGIC;    
	OUT2_N:    OUT    STD_LOGIC;    
	OUT3:      OUT    STD_LOGIC;    
	OUT3_N:    OUT    STD_LOGIC;    
	OUT4_N_OUT4B: OUT    STD_LOGIC;    
	OUT4_OUT4A: OUT    STD_LOGIC;    
	OUT5_N_OUT5B: OUT    STD_LOGIC;    
	OUT5_OUT5A: OUT    STD_LOGIC;    
	OUT6_N_OUT6B: OUT    STD_LOGIC;    
	OUT6_OUT6A: OUT    STD_LOGIC;    
	OUT7_N_OUT7B: OUT    STD_LOGIC;    
	OUT7_OUT7A: OUT    STD_LOGIC;    
	PAD:       IN     STD_LOGIC;    
	PD_N:      IN     STD_LOGIC;    
	REF_SEL:   IN     STD_LOGIC;    
	REFIN_N_REF2: IN     STD_LOGIC;    
	REFIN_REF1: IN     STD_LOGIC;    
	REFMON:    OUT    STD_LOGIC;    
	RESET_N:   IN     STD_LOGIC;    
	RSET:      INOUT  STD_LOGIC;    
	SCLK:      IN     STD_LOGIC;    
	SDIO:      INOUT  STD_LOGIC;    
	SDO:       OUT    STD_LOGIC;    
	STATUS:    OUT    STD_LOGIC;    
	SYNC_N:    IN     STD_LOGIC;    
	VCP:       IN     STD_LOGIC;    
	VS_1:      IN     STD_LOGIC;    
	VS_2:      IN     STD_LOGIC;    
	VS_3:      IN     STD_LOGIC;    
	VS_4:      IN     STD_LOGIC;    
	VS_5:      IN     STD_LOGIC;    
	VS_6:      IN     STD_LOGIC;    
	VS_7:      IN     STD_LOGIC;    
	VS_8:      IN     STD_LOGIC;    
	VS_9:      IN     STD_LOGIC;    
	VS_LVPECL_1: IN     STD_LOGIC;    
	VS_LVPECL_2: IN     STD_LOGIC);
end ad9517;
