-- generated by newgenasym Wed Jul 18 00:31:41 2012

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity adl5566 is
    port (    
	ENBL1:     IN     STD_LOGIC;    
	ENBL2:     IN     STD_LOGIC;    
	NC1:       INOUT  STD_LOGIC;    
	NC10:      INOUT  STD_LOGIC;    
	NC2:       INOUT  STD_LOGIC;    
	NC3:       INOUT  STD_LOGIC;    
	NC4:       INOUT  STD_LOGIC;    
	NC5:       INOUT  STD_LOGIC;    
	NC6:       INOUT  STD_LOGIC;    
	NC7:       INOUT  STD_LOGIC;    
	NC8:       INOUT  STD_LOGIC;    
	NC9:       INOUT  STD_LOGIC;    
	PAD:       IN     STD_LOGIC;    
	VCC_1:     IN     STD_LOGIC;    
	VCC_2:     IN     STD_LOGIC;    
	VCOM_1:    INOUT  STD_LOGIC;    
	VCOM_2:    INOUT  STD_LOGIC;    
	VIN_1:     IN     STD_LOGIC;    
	VIN_2:     IN     STD_LOGIC;    
	VIP_1:     IN     STD_LOGIC;    
	VIP_2:     IN     STD_LOGIC;    
	VON_1:     OUT    STD_LOGIC;    
	VON_2:     OUT    STD_LOGIC;    
	VOP_1:     OUT    STD_LOGIC;    
	VOP_2:     OUT    STD_LOGIC);
end adl5566;
