-- generated by newgenasym Mon Jul 12 20:03:18 2010

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity adp1740_v2 is
    port (    
	EN:        IN     STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	NC:        INOUT  STD_LOGIC;    
	PAD:       IN     STD_LOGIC;    
	PG:        OUT    STD_LOGIC;    
	SENSE:     IN     STD_LOGIC;    
	SS:        INOUT  STD_LOGIC;    
	VIN1:      IN     STD_LOGIC;    
	VIN2:      IN     STD_LOGIC;    
	VIN3:      IN     STD_LOGIC;    
	VIN4:      IN     STD_LOGIC;    
	VIN5:      IN     STD_LOGIC;    
	VOUT:      OUT    STD_LOGIC;    
	VOUT1:     OUT    STD_LOGIC;    
	VOUT2:     OUT    STD_LOGIC;    
	VOUT3:     OUT    STD_LOGIC;    
	VOUT4:     OUT    STD_LOGIC);
end adp1740_v2;
